RiscyOO: RISC-V Out-of-Order Processor

Tightly-coupled cache coherence unit for CVA6 using the ACE protocol

This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification

Bare Metal Compatibility Library for the Freedom Platform

Open Source Software for Developing on the Freedom E Platform - Deprecated

64-bit multicore RISC-V processor

The Splash-3 benchmark suite

gem5 simulation 4-core RISCV

Spike, a RISC-V ISA Simulator

This is a single cycle RISCV processor RTL implementation

32 bit pipelined RISC-V processor design and implementation for an FPGA.

An Open-Source Tool for CGRA Accelerators

An Open-Source Tool for CGRA Accelerators

chisel tutorial exercises and answers

OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.

ESnet SmartNIC hardware design repository.

An official code of Densely-packed Object Detection via Hard Negative-Aware Anchor Attention in WACV2022

This repository includ my image processing works

Intel Neuromorphic DNS Challenge

Implementation of "SpikeGPT: Generative Pre-trained Language Model with Spiking Neural Networks"

Verilog implementation of 16-bit multi-cycle RISC15 processor design

Single-Cycle RISC-V Processor in systemverylog

[ICCAD'22 TinyML Contest] Efficient Heart Stroke Detection on Low-cost Microcontrollers