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This is an official implementation for "Swin Transformer: Hierarchical Vision Transformer using Shifted Windows".

Python 13,690 2,042 Updated Jul 24, 2024

Official PyTorch implementation of A-ViT: Adaptive Tokens for Efficient Vision Transformer (CVPR 2022)

Python 147 13 Updated Jul 14, 2022

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

C 77 10 Updated Sep 27, 2024

SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)

C 23 3 Updated Jul 21, 2024

FPGA based Vision Transformer accelerator (Harvard CS205)

SystemVerilog 79 7 Updated Dec 11, 2023

Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.

Jupyter Notebook 25 5 Updated Apr 28, 2020

PYNQ support and examples for Kria SOMs

Jupyter Notebook 90 40 Updated Aug 20, 2024

[ICCV 2023] I-ViT: Integer-only Quantization for Efficient Vision Transformer Inference

Python 148 13 Updated Sep 2, 2024

An implementation of SIFT on GPU with OpenCL

Python 83 20 Updated Sep 21, 2018

Implementation of SIFT Algorithm on FPGA

Assembly 8 3 Updated Aug 24, 2017

An FPGA Accelerator for Transformer Inference

Jupyter Notebook 70 11 Updated Apr 29, 2022

Sub part of the SIFT algorithm as a Vitis HLS accelerated kernel

C 1 Updated Jan 15, 2021

ezSIFT: An easy-to-use standalone SIFT library written in C/C

C 95 28 Updated Jul 10, 2018

Machine learning on FPGAs using HLS

C 1,241 402 Updated Oct 7, 2024

Real Time SIFT implementation on FPGA

C 1 Updated Oct 29, 2019

Using Verilog to implement the SIFT algorithm into an FPGA for small robotic situations

36 17 Updated Dec 14, 2013

Post-Training Quantization for Vision transformers.

Python 178 25 Updated Jul 19, 2022

[HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design

Python 90 10 Updated Jun 27, 2023

A Comprehensive Dataflow Compiler for High-Level Synthesis

CMake 8 3 Updated Sep 6, 2024
Python 41 Updated Aug 7, 2023

You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

Verilog 100 8 Updated Mar 24, 2024

Segment Anything combined with CLIP

Python 329 23 Updated Feb 19, 2024

The repository provides code for running inference with the SegmentAnything Model (SAM), links for downloading the trained model checkpoints, and example notebooks that show how to use the model.

Jupyter Notebook 47,018 5,565 Updated Sep 18, 2024

[IJCAI 2022] FQ-ViT: Post-Training Quantization for Fully Quantized Vision Transformer

Python 302 48 Updated Apr 11, 2023

深度学习经典、新论文逐段精读

26,542 2,408 Updated Aug 8, 2024

CLIP (Contrastive Language-Image Pretraining), Predict the most relevant text snippet given an image

Jupyter Notebook 25,045 3,238 Updated Jul 23, 2024

XLS: Accelerated HW Synthesis

C 1,198 175 Updated Oct 8, 2024

Kria Vitis platforms and overlays

SystemVerilog 86 42 Updated Jul 3, 2024

Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts

C 82 13 Updated May 10, 2024
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