ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference

Contains the code examples from The UVM Primer Book sorted by chapters.

Repository to host and maintain scale-sim-v2 code

RISC-V SystemC-TLM simulator

You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network

Convolutional accelerator kernel, target ASIC & FPGA

clash-for-linux

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

A pre-RTL, power-performance model for fixed-function accelerators

We will be open sourcing a tool called FARSI (Facebook AR system investigator), a design space exploration framework. FARSI enables an agile and automated search of optimal hardware allocation and …

Unified Efficient Fine-Tuning of 100 LLMs (ACL 2024)

对llama3进行全参微调、lora微调以及qlora微调。

IC implementation of Systolic Array for TPU

End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.

🌟 The Multi-Agent Framework: First AI Software Company, Towards Natural Language Programming

Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.

A list of AI autonomous agents

This repo includes ChatGPT prompt curation to use ChatGPT better.

everything about llm & aigc

A repository hosting the source of SoC-tapeout babysitting tutorial.

Open-source high-performance RISC-V processor

Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.

🦜🔗 Build context-aware reasoning applications