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1. simple_fpu simple_fpu Public

   Fpu RTL for the IEEE 754 single precision standard, it includes addition, multiplication, division, square root and fp compare. It has some exception management.

   Verilog 2 1

2. Proyectos_functional_verification Proyectos_functional_verification Public

   SystemVerilog

3. async_fifo async_fifo Public

   A simple asynchronous fifo using a gray counter

   Verilog

4. DSE-for-approximate-adders DSE-for-approximate-adders Public

   This project uses a genetic algorithm to perform the design space exploration of a DUT. The DUT has some regular adders and the DSE replaces them by approximate adders while measuring the performance.

   Python