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1. CACTI-6.0 CACTI-6.0 Public

   ASIC simulation of Multi-ported Memory Module. And it can offer SRAM-based dual-port basic building block to support multiple read/write ports, and it can easily get the simulation result (like fre…

   C 15 5

2. CACTI-6.5 CACTI-6.5 Public

   This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condition circumstance.

   C 12 3

3. LVT_Writes_Method LVT_Writes_Method Public

   Live Value Table (LVT-based) techniques is increasing write ports method, and using table to track the latest address data.

   Verilog 2

4. Block_RAM_Module_FPGAs Block_RAM_Module_FPGAs Public

   Block RAMs (BRAMs) provide two types: two ports or dual-ports mode on FPGAs.

   Verilog 2

5. facebooc facebooc Public

   Forked from jserv/facebooc

   Yet another Facebook clone written in C

   C 1

6. 2R1W-Memory-Design 2R1W-Memory-Design Public

   Here offer 2R1W-based building block to proposed methodology to create multi-ported memory design. And different design to support more multi-ported level growth tree.

   Verilog 1