Interested in FPGA, VLSI, RISC-V, Accelerator and Digital Circuits Design.
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zcu104_test_pl_ddr Public
test pl ddr;run in c ; self defined memory controller for pl ddr
SystemVerilog UpdatedJul 25, 2024 -
nanoGPT Public
Forked from ReaLLMASIC/nanoGPTThe simplest, fastest repository for training/finetuning medium-sized GPTs.
Python MIT License UpdatedJun 28, 2024 -
spi-slave Public
Forked from nandland/spi-slaveSPI Slave for FPGA in Verilog and VHDL
Verilog MIT License UpdatedMay 11, 2024 -
You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.
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ZCU102-Pynq-3.0 Public
Forked from Arr-Dee/ZCU102-Pynq-3.0Fork from Kria-PYNQ repo. PYNQ support and examples for Kria SOMs, repurposed for ZCU102.
Jupyter Notebook Other UpdatedApr 3, 2023