Paper 2024/670

Secure Implementation of SRAM PUF for Private Key Generation

Raja Adhithan Radhakrishnan, Society for Electronic transactions and security
Abstract

This paper endeavors to securely implement a Physical Unclonable Function (PUF) for private data generation within Field-Programmable Gate Arrays (FPGAs). SRAM PUFs are commonly utilized due to their use of memory devices for generating secret data, particularly in resource constrained devices. However, their reliance on memory access poses side-channel threats such as data remanence decay and memory-based attacks, and the time required to generate secret data is significant. To address these issues, we propose implementing n cross-coupled inverters in Verilog to generate n secret bits, followed by syndrome for error correction hardcoded in the hardware itself. This approach improves side channel security and reduces time consumption, albeit at the expense of additional area utilization

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint.
Keywords
SRAM PUF-LDPC-Hashing
Contact author(s)
r rajaadhithan @ gmail com
History
2024-05-03: approved
2024-05-02: received
See all versions
Short URL
https://ia.cr/2024/670
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2024/670,
      author = {Raja Adhithan Radhakrishnan},
      title = {Secure Implementation of {SRAM} {PUF} for Private Key Generation},
      howpublished = {Cryptology {ePrint} Archive, Paper 2024/670},
      year = {2024},
      url = {https://eprint.iacr.org/2024/670}
}
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