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65 nm process

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The 65 nm process is an advanced lithographic node used in volume CMOS (MOSFET) semiconductor fabrication. Printed linewidths (i.e. transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm.[1]

Process node

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For comparison, cellular ribosomes are about 20 nm end-to-end. A crystal of bulk silicon has a lattice constant of 0.543 nm, so such transistors are on the order of 100 atoms across. By September 2007, Intel, AMD, IBM, UMC and Chartered were also producing 65 nm chips.

While feature sizes may be drawn as 65 nm or less, the wavelengths of light used for lithography are 193 nm and 248 nm. Fabrication of sub-wavelength features requires special imaging technologies, such as optical proximity correction and phase-shifting masks. The cost of these techniques adds substantially to the cost of manufacturing sub-wavelength semiconductor products, with the cost increasing exponentially with each advancing technology node. Furthermore, these costs are multiplied by an increasing number of mask layers that must be printed at the minimum pitch, and the reduction in yield from printing so many layers at the cutting edge of the technology. For new integrated-circuit designs, this factors into the costs of prototyping and production.

Gate thickness, another important dimension, is reduced to as little as 1.2 nm (Intel). Only a few atoms insulate the "switch" part of the transistor, causing charge to flow through it. This undesired leakage is caused by quantum tunneling. The new chemistry of high-κ gate dielectrics must be combined with existing techniques, including substrate bias and multiple threshold voltages, to prevent leakage from prohibitively consuming power.

IEDM papers from Intel in 2002, 2004, and 2005 illustrate the industry trend that the transistor sizes can no longer scale along with the rest of the feature dimensions (gate width only changed from 220 nm to 210 nm going from 90 nm to 65 nm technologies). However, the interconnects (metal and poly pitch) continue to shrink, thus reducing chip area and chip cost, as well as shortening the distance between transistors, leading to higher-performance devices of greater complexity when compared with earlier nodes. Intel's 65nm process has a transistor density of 2.08 million transistors per square milimeter (MTr/mm2).[2]

Example: Fujitsu 65 nm process

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  • Gate length: 30 nm (high-performance) to 50 nm (low-power)
  • Core voltage: 1.0 V
  • 11 Cu interconnect layers using nano-clustering silica as ultralow κ dielectric (κ=2.25)
  • Metal 1 pitch: 180 nm
  • Nickel silicide source/drain
  • Gate oxide thickness: 1.9 nm (n), 2.1 nm (p)

There are actually two versions of the process: CS200, focusing on high performance, and CS200A, focusing on low power.

[3][4]

Processors using 65 nm manufacturing technology

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References

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  1. ^ 2006 industry roadmap Archived September 27, 2007, at the Wayback Machine, Table 40a.
  2. ^ "Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review".
  3. ^ "Fujitsu Introduces World-class 65-Nanometer Process Technology for Advanced Server, Mobile Applications". Fujitsu (Press release). Sunnyvale, CA. September 20, 2005. Archived from the original on September 27, 2011. Retrieved August 10, 2008.
  4. ^ Kim, Paul (February 7, 2006). 65nm CMOS Process Technology (PDF). DesignCon. Fujitsu.
  5. ^ "ソニー、65nm対応の半導体設備を導入。3年間で2,000億円の投資". pc.watch.impress.co.jp. Archived from the original on August 13, 2016.
  6. ^ "OMAP 3 family of multimedia applications processors" (PDF). Texas Instruments. 2007. p. 1.
  7. ^ Gruener, Wolfgang (May 3, 2007). "AMD preps 65 nm Turion X2 processors". TG Daily. Archived from the original on September 13, 2007. Retrieved March 4, 2008.
  8. ^ "Microprocessor Elbrus-4C".
  9. ^ "ФГУ ФНЦ НИИСИ РАН: Разработка СБИС".

Sources

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Preceded by
90 nm 		MOSFET manufacturing processes Succeeded by
45 nm
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