أعاد Mabrains نشر هذا
Fresh graduate Electronics and Electrical Communications Engineering - Cairo university | PnR intern at ICpedia | AUC CND trainee
🎓 Excited to announce my graduation from the Faculty of Engineering, Cairo University! 🎓 I am thrilled to share that I have completed my Bachelor in Electronics and Electrical Communication Engineering with a distinction in my last year (87%) and an accumulative grade of Very Good with Honors (83%). My graduation project was marked with distinction, nearly achieving 100%. 📘 Graduation Project: Static Timing Analysis EDA Tool 📘 For my graduation project, sponsored by Mabrains, we implemented an open-source Static Timing Analysis (STA) tool to be integrated with OpenLane digital ASIC design. Here are some key highlights: ➡ Tool Implementation: Utilized Python language and Linux scripting for programming. ➡ Tool Usage: Applied for the STA step post-Synthesis to check timing and report violations. ➡ Tool Structure: Consists of 2 layers, Network analysis layer, and Core layer: - Network Analysis Layer: The ultimate goal of this layer is to extract the timing paths and their related information and feed them to the core layer. - This layer parses the Verilog netlist and maps the related information into a directed graph. The tool then extracts the timing paths from the graph using Breadth-First Search (BFS) algorithm in an efficient manner. - Core Layer: Calculates delay and generates timing reports for each path type using info from (.lib, SDC) files. - For each path type, timing is calculated using the info parsed from (.lib, SDC) files. - Report Generation: Provided pass/fail status for each path, offering clear insights into timing violations and ensuring design reliability. 👉My focus was on developing the network analysis layer, specializing in path extraction functions and graph creation, while ensuring seamless integration with the core timing calculations. 👉Checkout the GitHub repo: https://lnkd.in/dBshuHf5 We are excited to announce that we will continue to develop this tool further. Special thanks to Engineer Amro Tork for his invaluable guidance and support. We also appreciate our supervising professor at the university, Omar Nasr. I also want to extend my heartfelt gratitude to my teammates: Omar M., Eslam Samir, Ali Fathy, Karim Ragab, and Omar Mohamed for their collaboration and hard work. Thank you to everyone who supported me throughout this journey. I am excited about the opportunities ahead in the field of Electronics and Digital IC Design.