Bus bridges and other odds and ends

Repurposing existing HDL tools to help writing better code

Xilinx Virtual Cable Server for Raspberry Pi

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session

Extremely basic CortexM0 SoC based on ARM DesignStart Eval

experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.

This repository contains all labs done as a part of the Embedded Logic and Design course.

SPI ELF bootloader for Xilinx Microblaze processors

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

Bazel rules for Xilinx Vivado

Repository to store all design and testbench files for Senior Design

The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Very simple Cortex-M1 SoC design based on ARM DesignStart