Various HDL (Verilog) IP Cores

A FPGA core for a simple SDRAM controller.

SPD Reader & Writer with Software Write Protection capabilities supporting Arduino and SMBus

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

A re-imagining of the Amiga A2630 processor card.

RISC-V soft core running on Colorlight 5B-74B.

SDRAM controller optimized to a memory bandwidth of 316MB/s

Code examples of using STM32F429 for generating VGA image.

Kuchen Computer

RiscV based SOC for Qmtech Artix A7-200 board. Includes nekoRv: RISC-V 32 IM Zicsr core. And yes, it runs DOOM :)

Verilog SDR SDRAM controller for FPGA Xilinx and Lattice

Harsh Environment CubeSat Payload designed to evaluate three different manufacturing nodes SDR SDRAM technologies under space radiation conditions. It was developed for the FloripaSat-2 CubeSat mission.

An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

Projects using the Sipeed Tang Primer FPGA development board

Simple SDRAM Controller for DE10-Lite.

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

Verilog HDL implementation of SDRAM controller and SDRAM model

Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

SDRAM Tester implemented in FPGA