This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
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Jun 6, 2021 - Verilog
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gate-level-simulation
Here are 9 public repositories matching this topic...
Gate-Level Simulation on a GPU
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Nov 22, 2016 - C
USAGI is a Python script designed to automate the process of synthesizing and performing gate-level simulations for digital designs across a range of cycle times.
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Nov 21, 2024 - Python
This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C is used along with SystemC and SystemC-AMS libraries. Spring 2022
image-processing object-oriented systemc object-oriented-programming gate-level system-modeling systemc-ams gate-level-simulation rtl-design
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Jul 29, 2022 - C
A Parallel Discrete Event Simulation Engine with Examples
software-engineering multi-core partitioning metis conservative many-core discrete-event-simulation sychronization logic-simulator des-simulators queueing-networks pdes gate-level-simulation parallel-simulation parallel-discrete-event-simulation
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Oct 15, 2022 - C
Digital Logical Designs Course Projects
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Aug 19, 2022 - Verilog
FuzzyACOR-Algorithm (Adaptive fuzzy metaheuristic based optimisation algorithm)
layouts optimization layout ant-colony-optimization fuzzy-logic optimisation optimisation-algorithms gate-level ant-colony-optimisation electronics-design gate-level-simulation flipflop jkflipflop ant-colony-algorithm powerconsumption cmos-circuits adaptive-fuzzy-logic fuzzy-adaptive optimum-layout layout-design
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May 10, 2022 - MATLAB
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
c assembly spike verilog gtkwave soc yosys risc-v iverilog gate-level-simulation hardware-design chipcron
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May 8, 2024 - Verilog
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