EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

Very simple Cortex-M1 SoC design based on ARM DesignStart

5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.

This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..

RTL Design and Synthesis Workshop using Verilog with Sky130 Technology

VHDL tutorial

FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.

This repository contains different modules which execute arithmetic operations.

Full AES (Verilog)

VHDL controller for dynamic protocol switching (CAN, LIN, FlexRay).

A repo to store the coursework I do in college! 🎓

CipherX is a verification project for Advanced Encryption Standard (AES-128) using Universal Verification Methodology (UVM). It leverages Verilog, SystemVerilog, and Python to ensure robust encryption algorithm validation, integrating comprehensive UVM components and tests.

RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.

Computer Organization and Digital Design Projects - CS1050 - Semester 2

Placer and Router for standard cells

IP Module For LTC2311 ADC

This repository contains the design and implementation of a 4-bit Mealy Machine-based Overlapping Sequence Detector for detecting the sequence "1001" using 90nm CMOS technology and simulated in Cadence Virtuoso. The design employs SISO registers and master-negative edge-triggered D flip-flops within a Mealy machine architecture.

images equalizer in VHDL

a quick interface to any digital device that features magazines as a product

Educational repo for storing my practice sessions with digital systems as well as solutions to online courses or university courses I take. These implementations are done in VHDL or Verilog.