Python Control System : Create control loops and let the AI set the PID parameters

Inverted Pendulum in python with pybox2d. Fuzzy and PID simulation included.

Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.

This is an implementation of a simple CPU in Logisim and Verilog.

Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

Software for 3-axis machine control. It uses a Raspberry Pi with motor controllers and additional electronics. Features: visualization, GPIO emulation, touchscreen capability, and Cython optimization. Tested on Windows(visu) and Raspberry Pi OS. Under development with Pyside2 and OpenGl.

A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.

An automobile taillight control unit I created using VHDL, programmed to run on the Altera Cyclone V board.

simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL.

Implementation of a microprogrammed control unit for didactic purpose

My Solutions to Computer Architecture Course Practical Assignments

Using Python creating simulation of Control unit

The project involves designing a Simple RISC Computer (SRC) processor with 23 instructions, 32 registers, a control unit, data path, and memory components, aiming to create a functional CPU architecture capable of executing instructions.

This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.

16 bit processor designed in logisim

Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor

This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.