basys3-fpga

Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy. Implemented on a Basys3 Artix-7 FPGA with proper delays and hit signals.

cache-control lru-cache write-back basys3-fpga set-associative-cache four-way-set-associative

Updated Jul 22, 2020
Verilog

Harshp1802 / Fake-Currency-Detector

Star

Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB

matlab detection vhdl verilog bram fpga-programming basys3-fpga fake-currency block-ram

Updated Sep 30, 2020
VHDL

romybompart / Basys3-clock-alarm-with-buzzer

Star

Digital clock implemented in vhdl for the Basys 3 Board from Digilent.

clock vhd buzzer digit digital-clock basys3 digilent vhdl-code basys3-fpga basys3-clock-alarm buzzer-termination

Updated Dec 14, 2020
VHDL

praveenVnktsh / Hardware-Accelerated-Motion-Estimation-using-FSBM-and-FPGA

Star

FPGA Implementation of Full Search Block matching using an asynchronous handshake based FSM.

python fpga pixels vhdl motion estimation hdl vga verilog-hdl motion-estimation basys3 bram coe basys3-fpga macroblock

Updated Nov 2, 2020
VHDL

bingsen0806 / EE2026

Star

A Sound and Sight Entertainment System (SSES) implemented on Basys3 FPGA Board

pixel-art verilog vivado basys3 basys3-fpga

Updated May 13, 2021
Verilog

ColtonBeery / Digital_Clock

Star

Digital Clock for the Basys 3 FPGA

verilog verilog-hdl digital-clock basys3 basys3-fpga basys-3

Updated Mar 27, 2019
Verilog

ti-uni-bielefeld / logisim-evolution-basys3

Star

A set of scripts, manuals and patches to make synthesizing and downloading circuits from Logisim Evolution onto the Basys3 FPGA board on Linux easier and more seamless.

fpga vhdl university-project logisim basys3 fpga-board basys3-fpga logisim-evolution

Updated Oct 24, 2024
Shell

Yazmau / Verilog-Game-Tetris

Star

A tetris-game on screen using verilog.

hardware verilog tetris-game artix-7 basys3-fpga

Updated Jan 15, 2020
Verilog

Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

Star

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

verilog microprocessor vivado fibonacci-numbers 7-segment risc-v fibonacci-sequence basys3 vivado-hls artix-7 basys3-fpga single-cycle-processor basys3-fpga-board

Updated Dec 7, 2022
Tcl

ColtonBeery / Basys3_Camera_Driver

Star

Basys 3 driver for a Raspberry Pi NoIR 2.1 camera - COMPE470L class project

fpga camera verilog vga basys3 vga-driver basys3-fpga basys-3

Updated Apr 10, 2019
Verilog

martinKindall / 8-bit-multicycle-cpu

Star

Minimalist 8 bit multicycle RISC CPU

cpu fpga systemverilog 8-bit basys3 multicycle-processor 8-bit-cpu basys3-fpga 8-bit-computer multicycle

Updated Dec 14, 2022
SystemVerilog

yasanthaniroshan / NanoProcessor

Star

A Nanoprocessor designed to run on the Basys3 FPGA desgined using Xlinx Vivado with VHD using Registers, Add/Sub Unit, Decoders, Multiplexers which have been implemented seperately.