Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Sample 64-bit functional units #119

Open
wants to merge 3 commits into
base: 64bit
Choose a base branch
from

Conversation

LatifAkcayGithub
Copy link

Hello,

The request contains 64-bit compatible sample functional units.

Latif Akçay

@pjaaskel
Copy link
Contributor

Thanks for your contribution! Can you create a new hdb where these are included as FU entries so it is possible to use them in new 64b designs?

@LatifAkcayGithub
Copy link
Author

Hello Pekka,

So sorry. That's my first time doing such a thing.
I think, I did it now :)
Beside the FU codes, I have added a HDB and IC_Decoder_Plugin that generates 64-bit compatible decoder.
Please check it.

Thanks

Copy link
Contributor

@pjaaskel pjaaskel left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can you add a new systemtest that generates a 64b TTA with proge and simulates verifies the resulting RTL? There are similar systemtests which use ghdl optionally under systemtests and systemtests_long. Also be sure to run the old tests and make sure all of them pass. Did you see this page? https://github.com/cpc/tce/wiki/Contributor-Info

@@ -0,0 1,335 @@
-- Copyright (c) 2002-2009 Tampere University of Technology.
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Please check the copyright year, and the copyright also if you want to retain it. MIT license agreement is enough.

@@ -0,0 1,260 @@
-- Copyright (c) 2002-2009 Tampere University of Technology.
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Here also.

@@ -0,0 1,470 @@
-- Copyright (c) 2002-2009 Tampere University of Technology.
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

...

-- Designer: Latif AKCAY
-- University: Bayburt University, Istanbul Technical University, TURKEY.

-- LSU64 Operations
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Perhaps this comment is redundant thanks to the nice list of contants below.

@@ -0,0 1,166 @@
-- Copyright (c) 2002-2009 Tampere University of Technology.
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

...

data_out1_out <= "00000000000000000000000000000000" & data_out1_reg(31 downto 0); -- result has to be compatible with the currrent version of the operation!

end architecture rtl;

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

pls remove the empty lines

@@ -30,6 30,10 @@
* @author Vinogradov Viacheslav(added Verilog generating) 2012
* @note rating: red
*/

/*
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Please mind the 78 row size limit and also this type of comment belongs to git commit log, not in the source code. There you'd best describe what you did and preferably in more detail, why these changes were needed.

*fetchBlock);
toplevelBlock.netlist().connectPorts(
*ifetchCyclecountPort, *ttaCyclecountPort);
NetlistPort* ifetchLockcountPort = new NetlistPort(
"db_lockcnt", "32", 32, ProGe::BIT_VECTOR, HDB::OUT,
"db_lockcnt", "64", 64, ProGe::BIT_VECTOR, HDB::OUT,
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

You force 64 here, does 32 RTL generation still work? Did you run tools/scripts/compiletest.sh to check the tests? Do you have 'ghdl' installed so it runs the RTL tests?

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants