This is a project in development. It's basic goals are:

• Demonstrate an open source DDR3 SDRAM controller on a Kintex-7 board

• Repeat the demonstration using Yosys, an open source synthesis tool, followed by an open source place and route tool

I'll be building this project on an Enclustra KX2 daughter board, mounted on their Mercury ST1 Baseboards. Key peripherals in this setup include:

• UART/Debug bus/Console
  • ExBUS
  • WBConsole
• 4x 4x LEDs, 2x BTNs, and no switches
• QSPI flash
• DDR3
• GbE
• SD Card (DDR I/O)
  • Max clock = 50MHz
  • TXS02612RTWR, only one SD card connected
  • GPIO wires include: SD Reset, SD card reset, Clock locked

Once these have been implemented, the project will be a success. The following additional peripherals may also be implemented as time and necessity allow.

• I2C

  • RTC: ISL12020MIRZ
  • Secure EEPROM: ATSHA204A or DS28CN01U
  • Si5338 ? PCI3, Ethernet, GbE, broadcast audio, ???
  • Si570: 10MHz->1.4GHz I2C Programmable XO/VCXO
  • I2C Multiplexers: NLASB3157DFT2G--is a silicon switch (?)

• SPI?

• SATA. My SATA project isn't (currently) in a usable state. Until it gets there, we won't have SATA control on this board. Still, this board is a key piece of test hardware for testing the SATA controller.

  No, the Enclustra board doesn't come with a SATA capability. However, I have an FPGADrive FMC board attached, which should allow SATA development.

• (2nd GbE) This board has two Gb Ethernet ports on it. At present, I have no plans for the second port. I'm open to ideas, however.

• (Display Port?) I've never touched the display port protocol before. Whether or not I can do anything with it, or even whether or not I have the time and priority to do so remains to be determined.

• (HDMI: Not connected). Don't ask me why, but Enclustra never connected the HDMI port. (I think they ran out of high speed IO or some such. I'm not certain.)

1. EXBUS

   Required to load programs for the CPU

   STATUS: PASS.

2. LED/Switch

   Used as a test of the EXBUS

   STATUS: PASS

3. Flash

   Load a design, configure design from flash. First CPU loads come from flash.

   STATUS: PASS. However, loading a 6MB design into the flash is horribly slow.

4. ICAPE Controller

   Status: PASS

   Note that to restart the design, you'll have to take the flash out of XiP mode.

5. CPU

   CPU check will be the first program. Other programs have included Hello World, and an MDIO register check.

   Status: PASS

6. MDIO Dump

   Can the management registers be read from the Ethernet PHY? Do these registers make sense?

   STATUS: PASS.

   Given that there are two Ethernet ports on this board, and further that the design only connects one of these ports to logic, accessing the MDIO registers is an important part of knowing whether or not the ethernet cable is plugged into the correct port.

7. Ping

   Can the board be "pinged"? This includes a test of the automatic ARP handling. The test depends upon the ability to load an FPGA design, but does not depend on the CPU.

   STATUS: PASS

8. Network debugging protocol (Optional test)

   This will test whether or not memory can be read and/or written from an external host, via specially crafted UDP/IP packets. This network packet protocol blows the doors off of the UART alternative, although it is a bit harder to setup and get working initially. For example, both ARP and ICMP handling have to work automatically and without CPU involvement first.

   STATUS: PASS.

9. DDR3 SDRAM memory

   This test will first verify that the onboard memory works with Xilinx's DDR3 memory controller, commonly known as "the MIG".

   Once hooked up, the MIG will be subjected to a memory test. Portions of the test have been drafted already.

   Status: PASS.

10. OpenSource DDR3 SDRAM memory

If and when the MIG DDR3 SDRAM test passes, we'll move on to testing the open source DDR3 memory controller.

STATUS: Passes an initial test. More thorough tests ongoing.

11. Open source place and route

    Can the design be built using all open-source tools, instead of via Vivado?

12. SDIO (Optional test)

    Requires both the CPU and memory

    STATUS: Pass.

13. Network CPU Access (Optional test)

    Can the CPU send and receive packets?

    STATUS: Not yet tested. Pending a software driver.

14. I2C Testing (Optional test)

This project is a work in progress.

The current project status is maintained pictorially here, in the doc/ directory. The project has been assembled, and all of the key component tests pass--as noted above and in the diagram.

At present, the design is configured to use Xilinx's MIG controller. It works in this configuration. The next step will involve running memory performance tests, and then moving from Xilinx's controller to the open source uberDDR3 controller.