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Working from home
Hardware design engineer focused on implementing logical circuits using VHDL, and Verilog.
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Tarbiat Modarres University
- Tehran
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UBX_parser
UBX_parser Publicthis repo containt rtl code which parse ubx packet came from uart
Verilog
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Python_Serial_plotter
Python_Serial_plotter PublicForked from mealadmmb/Python_Serial_plotter
It Recieve the fft of data from FPGA through Uart Serial and then plot it continusly.
Python
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