VMEbus

VMEbus (Versa Module Eurocard bus) is a computer bus standard physically based on Eurocard sizes.

VME64 crate with, from left, an ADC module, a scaler module and a processor module

History

In 1979, during development of the Motorola 68000 CPU, one of their engineers, Jack Kister, decided to set about creating a standardized bus system for 68000-based systems. The Motorola team brainstormed for days to select the name VERSAbus. VERSAbus cards were large, 370 by 230 mm (14 1⁄2 by 9 1⁄4 in), and used edge connectors. Only a few products adopted it, including the IBM System 9500 instrument controller and the Automatix robot and machine vision systems.

VERSAbus memory card

Kister was later joined by John Black, who refined the specifications and created the VERSAmodule product concept. A young engineer working for Black, Julie Keahey designed the first VERSAmodule card, the VERSAbus Adaptor Module, used to run existing cards on the new VERSAbus. Sven Rau and Max Loesel of Motorola-Europe added a mechanical specification to the system, basing it on the Eurocard standard that was then late in the standardization process. The result was first known as VERSAbus-E but was later renamed to VMEbus, for VERSAmodule Eurocard bus (although some refer to it as Versa Module Europa).

At this point, a number of other companies involved in the 68000's ecosystem agreed to use the standard, including Signetics, Philips, Thomson, and Mostek. Soon it was officially standardized by the IEC as the IEC 821 VMEbus and by ANSI and IEEE as ANSI/IEEE 1014-1987.

The original standard was a 16-bit bus, designed to fit within the existing Eurocard DIN connectors. However, there have been several updates to the system to allow wider bus widths. The current VME64 includes a full 64-bit bus in 6U-sized cards and 32-bit in 3U cards. The VME64 protocol has a typical performance of 40 MB/s. Other associated standards have added hot-swapping (plug-and-play) in VME64x, smaller 'IP' cards that plug into a single VMEbus card, and various interconnect standards for linking VME systems together.

In the late 1990s, synchronous protocols proved to be favourable. The research project was called VME320. The VITA Standards Organization called for a new standard for unmodified VME32/64 backplanes. The new 2eSST protocol was approved in ANSI/VITA 1.5 in 1999.

Over the years, many extensions have been added to the VME interface, providing 'sideband' channels of communication in parallel to VME itself. Some examples are IP Module, RACEway Interlink, SCSA, Gigabit Ethernet on VME64x Backplanes, PCI Express, RapidIO, StarFabric and InfiniBand.

VMEbus was also used to develop closely related standards, VXIbus and VPX. The VMEbus had a strong influence on many later computer buses such as STEbus.

VME early years

The architectural concepts of the VMEbus are based on VERSAbus, developed in the late 1970s by Motorola. This was later renamed "VME", short for Versa Module European, by Lyman (Lym) Hevle, then a VP with the Motorola Microsystems Operation. (He was later the founder of the VME Marketing Group, itself subsequently renamed to VME International Trade Association, or VITA).

John Black of Motorola, Craig MacKenna of Mostek and Cecil Kaplinsky of Signetics developed the first draft of the VMEbus specification. In October 1981, at the System '81 trade show in Munich, West Germany, Motorola, Mostek, Signetics/Philips, and Thomson CSF announced their joint support of the VMEbus. They also placed Revision A of the specification in the public domain.

In 1985, Aitech developed, under contract for US Army TACOM, the first conduction-cooled 6U VMEbus board. Although electrically providing a compliant VMEbus protocol interface, mechanically, this board was not interchangeable for use in air-cooled lab VMEbus development chassis.

In late 1987, a technical committee was formed under VITA under the direction of IEEE to create the first military, conduction-cooled 6U × 160 mm, fully electrically and mechanically compatible, VMEbus board co-chaired by Dale Young (DY4 Systems) and Doug Patterson (Plessey Microsystems, then Radstone Technology). ANSI/IEEE-1101.2-1992 was later ratified and released in 1992 and remains in place as the conduction-cooled, international standard for all 6U VMEbus products.

In 1989, John Peters of Performance Technologies Inc. developed the initial concept of VME64: multiplexing address and data lines (A64/D64) on the VMEbus. The concept was demonstrated the same year and placed in the VITA Technical Committee in 1990 as a performance enhancement to the VMEbus specification.

In 1993, new activities began on the base-VME architecture, involving the implementation of high-speed serial and parallel sub-buses for use as I/O interconnections and data mover subsystems. These architectures can be used as message switches, routers and small multiprocessor parallel architectures.

VITA's application for recognition as an accredited standards developer organization of ANSI was granted in June 1993. Numerous other documents ( including mezzanine, P2 and serial bus standards) have been placed with VITA as the Public Domain Administrator of these technologies.

Evolution of VME

Topology	Year	Bus cycle	Maximum speed (MB/s)
VMEbus32 Parallel Bus Rev. A	1981	BLT	40
VMEbus IEEE-1014	1987	BLT	40
VME64	1994	MBLT	80
VME64x	1997	2eVME	160
VME320	1997	2eSST	320

Description

In many ways the VMEbus is equivalent or analogous to the pins of the 68000 run out onto a backplane.

However, one of the key features of the 68000 is a flat 32-bit memory model, free of memory segmentation and other "anti-features". The result is that, while VME is very 68000-like, the 68000 is generic enough to make this not an issue in most cases.

Like the 68000, VME uses separate 32-bit data and address buses. The 68000 address bus is actually 24-bit and the data bus 16-bit (although it is 32/32 internally) but the designers were already looking towards a full 32-bit implementation.

In order to allow both bus widths, VME uses two different Eurocard connectors, P1 and P2. P1 contains three rows of 32 pins each, implementing the first 24 address bits, 16 data bits and all of the control signals. P2 contains one more row, which includes the remaining 8 address bits and 16 data bits.

A block transfer protocol allows several bus transfers to occur with a single address cycle. In block transfer mode, the first transfer includes an address cycle and subsequent transfers require only data cycles. The slave is responsible for ensuring that these transfers use successive addresses.

Bus masters can release the bus in two ways. With Release When Done (RWD), the master releases the bus when it completes a transfer and must re-arbitrate for the bus before every subsequent transfer. With Release On Request (ROR), the master retains the bus by continuing to assert BBSY* between transfers. ROR allows the master to retain control over the bus until a Bus Clear (BCLR*) is asserted by another master that wishes to arbitrate for the bus. Thus a master that generates bursts of traffic can optimize its performance by arbitrating for the bus on only the first transfer of each burst. This decrease in transfer latency comes at the cost of somewhat higher transfer latency for other masters.

Address modifiers are used to divide the VME bus address space into several distinct sub-spaces. The address modifier is a 6 bit wide set of signals on the backplane. Address modifiers specify the number of significant address bits, the privilege mode (to allow processors to distinguish between bus accesses by user-level or system-level software), and whether or not the transfer is a block transfer. Below is an incomplete table of address modifiers:

Hex Code	Function	Explanation
3f	Standard Supervisory block transfer	Block transfer A24, privileged
3e	Standard Supervisory Program access	A24 instruction access, privileged
3d	Standard Supervisor Data Access	A24 data access, privileged
3b	Standard Non-privileged block transfer	A24 block transfer for normal programs
3a	Standard Non-privileged Program access	A24 instruction access, non-privileged
39	Standard non-privileged Data Access	A24 data access, non-privileged
2d	Short supervisory Access	A16 privileged access.
29	Short non-privileged Access	A16 non-privileged access.
0f	Extended supervisory Block transfer	A32 privileged block transfer.
0e	Extended supervisory Program access	A32 privileged instruction access.
0d	Extended supervisory Data Access.	A32 privileged data access.
0b	Extended Non-privileged Block transfer	A32 non-privileged block transfer.
0a	Extended Non-privileged Program access	A32 non-privileged instruction access.
09	Extended non-privileged data access.	A32 non-privileged data access.
Note		An as in A16, A24, A32 refers to the width of the address

On the VME bus, all transfers are DMA and every card is a master or slave. In most bus standards, there is a considerable amount of complexity added in order to support various transfer types and master/slave selection. For instance, with the ISA bus, both of these features had to be added alongside the existing "channels" model, whereby all communications was handled by the host CPU. This makes VME considerably simpler at a conceptual level while being more powerful, though it requires more complex controllers on each card.

Development tools

When developing and/or troubleshooting the VME bus, examination of hardware signals can be very important. Logic analyzers and bus analyzers are tools that collect, analyze, decode, store signals so people can view the high-speed waveforms at their leisure.

VITA offers a comprehensive FAQ to assist with the front end design and development of VME systems.

Computers using a VMEbus

Computers using VMEbus include:

• HP 743/744 PA-RISC Single-board computer
• Sun-2 through Sun-4
• HP 9500 Industrial Workstations
• Atari TT030 and Atari MEGA STE
• Motorola MVME
• Symbolics
• Advanced Numerical Research and Analysis Group's PACE.
• ETAS ES1000 Rapid Prototyping System
• Several Motorola 88000-based Data General AViiON computers
• Early Silicon Graphics MIPS-based systems including Professional IRIS, Personal IRIS, Power Series, and Onyx systems
• Convergent Technologies MightyFrame

Pinout

Seen looking into backplane socket.

P1

Pin	a	b	c
1	D00	BBSY*	D08
2	D01	BCLR*	D09
3	D02	ACFAIL*	D10
4	D03	BG0IN*	D11
5	D04	BG0OUT*	D12
6	D05	BG1IN*	D13
7	D06	BG1OUT*	D14
8	D07	BG2IN*	D15
9	GND	BG2OUT*	GND
10	SYSCLK	BG3IN*	SYSFAIL*
11	GND	BG3OUT*	BERR*
12	DS1*	BR0*	SYSRESET*
13	DS0*	BR1*	LWORD*
14	WRITE*	BR2*	AM5
15	GND	BR3*	A23
16	DTACK*	AM0	A22
17	GND	AM1	A21
18	AS*	AM2	A20
19	GND	AM3	A19
20	IACK*	GND	A18
21	IACKIN*	SERCLK	A17
22	IACKOUT*	SERDAT*	A16
23	AM4	GND	A15
24	A07	IRQ7*	A14
25	A06	IRQ6*	A13
26	A05	IRQ5*	A12
27	A04	IRQ4*	A11
28	A03	IRQ3*	A10
29	A02	IRQ2*	A09
30	A01	IRQ1*	A08
31	−12V	5VSTDBY	12V
32	5V	5V	5V

P2

Pin	a	b	c
1	User Defined	5V	User Defined
2	User Defined	GND	User Defined
3	User Defined	RESERVED	User Defined
4	User Defined	A24	User Defined
5	User Defined	A25	User Defined
6	User Defined	A26	User Defined
7	User Defined	A27	User Defined
8	User Defined	A28	User Defined
9	User Defined	A29	User Defined
10	User Defined	A30	User Defined
11	User Defined	A31	User Defined
12	User Defined	GND	User Defined
13	User Defined	5V	User Defined
14	User Defined	D16	User Defined
15	User Defined	D17	User Defined
16	User Defined	D18	User Defined
17	User Defined	D19	User Defined
18	User Defined	D20	User Defined
19	User Defined	D21	User Defined
20	User Defined	D22	User Defined
21	User Defined	D23	User Defined
22	User Defined	GND	User Defined
23	User Defined	D24	User Defined
24	User Defined	D25	User Defined
25	User Defined	D26	User Defined
26	User Defined	D27	User Defined
27	User Defined	D28	User Defined
28	User Defined	D29	User Defined
29	User Defined	D30	User Defined
30	User Defined	D31	User Defined
31	User Defined	GND	User Defined
32	User Defined	5V	User Defined

P2 rows a and c can be used by a secondary bus, for example the STEbus.

See also

• Data acquisition
• VPX
• VXS
• Futurebus
• CompactPCI
• CAMAC
• FPDP
• List of device bandwidths

External links

• VITA
• VMEBUS TECHNOLOGY FAQ
• Next Generation VME
• VME bus pinout and signals