Tech Lead Firmware Engineer (DDR technologies)
Astera Labs
Santa Clara, CA
See who Astera Labs has hired for this role
Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
Job Description
As an Astera Labs Tech Lead Firmware Engineer, you will be designing and developing Firmware for enabling DDR technologies for future looking products defined by Astera Labs CXL memory solutions.
Basic Qualifications
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ and non-binary people, veterans, parents, and individuals with disabilities.
Job Description
As an Astera Labs Tech Lead Firmware Engineer, you will be designing and developing Firmware for enabling DDR technologies for future looking products defined by Astera Labs CXL memory solutions.
Basic Qualifications
- Bachelor’s in Electrical engineering / Electronics / Computer Science or related fields.
- 5 years of experience in developing Firmware using C in Embedded environments.
- Good knowledge in DDR Technology internals (DDR Training, DDR RAS, PMIC, RCD etc.)
- Ability to debug DDR related issues.
- Post-Silicon bring up and validation of DDR memory interfaces
- Experience working with cross-functional teams and partners.
- Pre-Silicon DDR bring up experience is a plus
- Experience with RDIMMs, DDR controller/PHY tuning is a plus
- Knowledge of Server memory performance and stability tuning for latency and bandwidth is a plus
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ and non-binary people, veterans, parents, and individuals with disabilities.
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Seniority level
Mid-Senior level -
Employment type
Full-time -
Job function
Engineering and Information Technology -
Industries
Semiconductor Manufacturing
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