RISC-V Design Verification Engineer (Intermediate-Staff)

RISC-V Design Verification Engineer

Onsite preferred in either Portland (USA) or Vancouver (Canada), or remote for the right candidate.

Intermediate experience level: $100k - $150k

Senior to Staff experience levels: $150k - $250k

Corporate Introduction

As a founding premier member of RISC-V International, Andes is the leading supplier and technological innovator in the RISC-V market with a wide range of processor products fulfilling performance/area/power requirements. Andes has perfected the technology of quick and efficient design of custom extensions to its proprietary CPU. With over 10 billion cumulative shipments of SoCs embedded with Andes CPU IP, Andes products have covered audio, Bluetooth, gaming, GPS, machine learning, MCU and more. Our design innovation enables us to quickly adapt to the rapidly evolving demands of RISC-V customers.

Founded in 2005, Andes yearly revenue has tripled in size from $10 million in 2017 to $30 million in 2021. Andes was ranked among "100 Fastest-Growing Companies" in 2020 by CommonWealth Magazine. Headquartered in Taiwan, Andes is capitalizing on its current growth by branching out its offices to the US and Canada to expand on its current 300 employee workforce. Employees are valued as the key ingredient to the success of the company. They will have an opportunity to create a strong and positive impact on the company, where feedback is encouraged and implemented.

Role

You will be a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.

As a senior member of this team, you will help guide verification methodologies, analyze problems and devise best QoR solutions. You will participate in engineering discussions and be expected to drive analysis and propose directions. Applicants of this role would be diligent, detail oriented and have a penchant for creating high-quality results efficiently. You should also admire technical advances, CPU architecture and have a keen interest in tackling present day verification problems.

Daily activity includes:

• Communication with peers to discuss technical details
• Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them
• Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports
• Hands-on verification work including verification regression management, debugging and bug-reports
• Provide technical guidance to junior members of the team
• Technical documentation

Technical Requirements

• Bachelor’s or Master’s degree in related engineering field
• Strong communication skills
• Experience using Verilog, System Verilog
• Strong mastery using Unix and scripting languages such as make, shell, perl or python

Desirable Skills

• Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug)
• Experience with ground-up test-benches development
• Experience with functional coverage-driven verification
• Familiar with stimulus generation for constrained random simulation. Experience coding in assembly languages
• Experience in UVM, formal, coverage grading, coverage analysis, bug tracking
• Patience and good leadership skills
• Strong desire to learn and willing to devote extra effort to achieve perfection
• Strong team player and possess a positive attitude